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학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
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논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2019.5
- 수록면
- 191 - 196 (6page)
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초록· 키워드
오류제보하기
Phase-locked loops (PLLs) are the key technique for inverters to be synchronized with the PCC voltage. Typically, in the single-phase applications, the delaybased PLL is being widely used. However, for nowadays applications where the inverter may be connected to the PCC with large grid impedance, the inverter performance can be endangered, and harmonics or even instabilities are aroused. Although there are some relevant literatures, the solutions for solving the adverse impacts of delay-PLL on the system performance are still not well documented. Therefore, this paper aims to study the limitations of delay-based PLL and provide an improved approach. Through the inverter output impedance modelling, the reason why the delay-based PLL causes the instability in the weak grid case has been clearly explained. Then, the way to solve the instability caused by the PLL has been discussed, and an improved delay-based PLL has been proposed to improve the weak grid compatibility of inverters. The single-phase inverter system can then work well when the grid impedance varies widely.
목차
Abstract
I. INTRODUCTION
II. OUTPUT IMPEDANCE MODEL OF GRID-CONNECTED INVERTERS IN THE WEAK GRID CASE
III. REASONS FOR INSTABILITY IN THE WEAK GRID CASE
IV. PROPOSED IMPROVED PLL BASED ON LOW-PASS FILTER AND DESIGN
V. VERIFICATIONS
VI. CONCLUSIONS
REFERENCES
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