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This paper proposes an algorithm that reduces the conversion time of a single-slope A/D converter (SSADC) that has nbit resolution, which typically is limited by conversion time taking up to 2n clock cycles for an operation. To improve this situation, we have researched a novel hybrid-type A/D converter that consists of a pseudo-pipeline A/D converter and a conventional SSADC. The pseudo-pipeline A/D converter, using a single-stage of analog components, determines the most significant bits (MSBs) or upper bits and the conventional SSADC determines the remaining bits. Therefore, the modified SSADC, similar to the hybrid-type A/D converter, is able to significantly reduce the conversion time because the pseudopipeline A/D converter, which determines the MSBs (or upper bits), does not rely on a clock. The proposed A/D converter was designed using a 0.35-μm 2-poly 4-metal standard complementary metal oxide semiconductor (CMOS) technology process; additionally, its characteristics were simulated.
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참고문헌 (8)
참고문헌 신청
A. Mahdy / 2008 / A high-speed analog comparator in 0.5 μm CMOS technology / National Radio Science Conference NRSC 2008 : 1 ~ 7
C. H. Kuo / 2010 / Bias-and-input interchanging technique for cyclic/pipelined ADCs with opamp sharing / IEEE Transactions on Circuits and Systems II 57 (3) : 168 ~ 172
I. Y. Oh / 2009 / Dynamic bias circuit of CMOS power amplifier sensing dissipated signals / IET Electronics Letters 45 (14) : 744 ~ 746
K. B Klaassen / 1978 / A fast and unilateral monolithic switch for analog signals / IEEE Journal of Solid-State Circuits 13 (2) : 258 ~ 261
M. J. Cabebe / 2013 / Design tradeoffs in a 0. 5 V 65 nm CMOS folded cascade OTA / IEEE TENCON Spring Conf 2013 : 293 ~ 297
C. H. Kuo / 2010 / Bias-and-input interchanging technique for cyclic/pipelined ADCs with opamp sharing / IEEE Transactions on Circuits and Systems II 57 (3) : 168 ~ 172
I. Y. Oh / 2009 / Dynamic bias circuit of CMOS power amplifier sensing dissipated signals / IET Electronics Letters 45 (14) : 744 ~ 746
K. B Klaassen / 1978 / A fast and unilateral monolithic switch for analog signals / IEEE Journal of Solid-State Circuits 13 (2) : 258 ~ 261
M. J. Cabebe / 2013 / Design tradeoffs in a 0. 5 V 65 nm CMOS folded cascade OTA / IEEE TENCON Spring Conf 2013 : 293 ~ 297
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