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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.22 No.4
- 발행연도
- 2022.8
- 수록면
- 266 - 274 (9page)
- DOI
- 10.5573/JSTS.2022.22.4.266
이용수
초록· 키워드
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In this paper, an investigation has been performed to analyze the relation between on-current (I<SUB>on</SUB>) and gate work function variation (WFV) in the tunnel field-effect transistor (TFET) with help of technology computer-aided design (TCAD) simulation. Comparing the I<SUB>on</SUB> of metal-oxide-semiconductor field-effect transistor (MOSFET) and TFET, it is observed that the quantized current level of TFET is depending on channel bias conditions and width of channel. Therefore, we analyze this current quantization within three categorizations. Firstly, the I<SUB>on</SUB> is quantized by applied level of high gate bias (V<SUB>GS</SUB>). At high V<SUB>GS</SUB>, the I<SUB>on </SUB>is quantized well following gate WF value near the source-side because the tunnel barrier is made in the specific area by junction between gate and source. However, at low V<SUB>GS</SUB>, a lot of current levels are confirmed because almost half of the channel is affected by WFV due to the large tunneling width. Secondly, the quantized I<SUB>on</SUB> variation by WFV is also affected by level of V<SUB>DS</SUB>. Because the influence of the channel potential is differed by induced electron density. Finally, the I<SUB>on</SUB> is quantized by width of device. Because, considering metal grain size, the WF value near the source-side is determined only several levels. Then, related with the width, we quantitatively analyzed the quantization of I<SUB>on</SUB>, and based on the probability of WFVs, it is confirmed that the phenomenon of current quantization in TFET is predictable.
목차
Abstract
I. INTRODUCTION
II. DEVICE STRUCTURE AND SIMULATION METHOD
III. RESULTS
IV. CONCLUSIONS
REFERENCES
참고문헌 (41)
참고문헌 신청
W. Y. Choi, B. G. Park, J. D. Lee, and T. J. K. Liu, “Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec,” IEEE Electron Device Lett., Vol. 28, No. 8, pp. 743-745, 2007.
K. Bernstein, R. K. Cavin, W. Porod, A. Seabaugh, and J. Welser, “Device and architecture outlook for beyond CMOS switches,” Proc. IEEE, Vol. 98, No. 12, pp. 2169-2184, 2010.
J. H. Kim, S. Kim, and B. G. Park, “Double-Gate TFET With Vertical Channel Sandwiched by Lightly Doped Si,” IEEE Trans. Electron Devices, Vol. 66, No. 4, pp. 1656-1661, 2019.
A. C. Seabaugh and Q. Zhang, “Low-voltage tunnel transistors for beyond CMOS logic,” Proc. IEEE, Vol. 98, No. 12, pp. 2095-2110, 2010.
P. Y. Wang and B. Y. Tsui, “Band engineering to improve average subthreshold swing by suppressing low electric field band-to-band tunneling with epitaxial tunnel layer tunnel FET structure,” IEEE Trans. Nanotechnol., Vol. 15, No. 1, pp. 74-79, 2016.
K. Bernstein, R. K. Cavin, W. Porod, A. Seabaugh, and J. Welser, “Device and architecture outlook for beyond CMOS switches,” Proc. IEEE, Vol. 98, No. 12, pp. 2169-2184, 2010.
J. H. Kim, S. Kim, and B. G. Park, “Double-Gate TFET With Vertical Channel Sandwiched by Lightly Doped Si,” IEEE Trans. Electron Devices, Vol. 66, No. 4, pp. 1656-1661, 2019.
A. C. Seabaugh and Q. Zhang, “Low-voltage tunnel transistors for beyond CMOS logic,” Proc. IEEE, Vol. 98, No. 12, pp. 2095-2110, 2010.
P. Y. Wang and B. Y. Tsui, “Band engineering to improve average subthreshold swing by suppressing low electric field band-to-band tunneling with epitaxial tunnel layer tunnel FET structure,” IEEE Trans. Nanotechnol., Vol. 15, No. 1, pp. 74-79, 2016.
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