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학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.22 No.6
- 발행연도
- 2022.12
- 수록면
- 436 - 451 (16page)
- DOI
- 10.5573/JSTS.2022.22.6.436
이용수
초록· 키워드
오류제보하기
Noise-shaping successive-approximation-register (NS-SAR) ADCs have become one of the most promising candidates for high-resolution data converters over the past decade. This is due to the fact that they combine the advantages of delta-sigma modulation and SAR ADCs. In this hybrid architecture, the quantizer and residue feedback DAC can be replaced by SAR, a replacement which achieves high SNR while also benefiting from superior power efficiency and low cost. For NS-SAR ADCs, various implementations of loop filters for residue processing exist that can realize the noise transfer function (NTF) for NS effects. In addition, many noise reduction techniques have been proposed that suppress additional noises not shaped by NTF. This paper describes the basics of NS-SAR ADCs while also reviewing noise reduction techniques, which include the implementation of a loop filter for residue handling, kT/C noise rejection, and capacitive DAC mismatch error shaping. It also outlines advanced architectures that can overcome the limitations of NS-SAR ADCs.
목차
Abstract
I. INTRODUCTION
II. BASIC OF NOISE-SHAPING (NS) SAR ADCS
III. NOISE REDUCTION TECHNIQUES WITH RESIDUE PROCESSING
IV. ADDITIONAL NOISE AND ERROR REDUCTION TECHNIQUES
V. ADVANCED ARCHITECTURES (FUTURE TRENDS)
VI. CONCLUSION
REFERENCES
참고문헌 (51)
참고문헌 신청
J. A. Fredenburg and M. P. Flynn, "A 90-MS/s 11-MHz-Bandwidth 62-dB SNDR Noise-Shaping SAR ADC," IEEE Journal of Solid-State Circuits, vol. 47, no. 12, pp. 2898-2904, 2012.
Z. Chen, M. Miyahara, and A. Matsuzawa, "A 9.35-ENOB, 14.8 fJ/conv.-step Fully-Passive Noise-Shaping SAR ADC," in 2015 Symposium on VLSI Circuits (VLSI Circuits), 2015, pp. C64-C65.
Z. Chen, M. Miyahara, and A. Matsuzawa, "A 2nd Order Fully-Passive Noise-Shaping SAR ADC with Embedded Passive Gain," in 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2016, pp. 309-312.
W. Guo and N. Sun, "A 12b-ENOB 61μW Noise-Shaping SAR ADC with a Passive Integrator," in ESSCIRC Conference 2016: 42nd European Solid- State Circuits Conference, 2016, pp. 405-408.
K. Obata, K. Matsukawa, T. Miki, Y. Tsukamoto, and K. Sushihara, "A 97.99 dB SNDR, 2 kHz BW, 37.1 μW Noise-Shaping SAR ADC with Dynamic Element Matching and Modulation Dither Effect," in 2016 IEEE Symposium on VLSI Circuits (VLSICircuits), 2016, pp. 1-2.
Z. Chen, M. Miyahara, and A. Matsuzawa, "A 9.35-ENOB, 14.8 fJ/conv.-step Fully-Passive Noise-Shaping SAR ADC," in 2015 Symposium on VLSI Circuits (VLSI Circuits), 2015, pp. C64-C65.
Z. Chen, M. Miyahara, and A. Matsuzawa, "A 2nd Order Fully-Passive Noise-Shaping SAR ADC with Embedded Passive Gain," in 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2016, pp. 309-312.
W. Guo and N. Sun, "A 12b-ENOB 61μW Noise-Shaping SAR ADC with a Passive Integrator," in ESSCIRC Conference 2016: 42nd European Solid- State Circuits Conference, 2016, pp. 405-408.
K. Obata, K. Matsukawa, T. Miki, Y. Tsukamoto, and K. Sushihara, "A 97.99 dB SNDR, 2 kHz BW, 37.1 μW Noise-Shaping SAR ADC with Dynamic Element Matching and Modulation Dither Effect," in 2016 IEEE Symposium on VLSI Circuits (VLSICircuits), 2016, pp. 1-2.
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