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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.23 No.5
- 발행연도
- 2023.10
- 수록면
- 265 - 272 (8page)
- DOI
- 10.5573/JSTS.2023.23.5.265
이용수
초록· 키워드
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This paper presents a 2<SUP>nd</SUP> order modified feed-forward (FF) delta-sigma modulator. To reduce power consumption, the proposed analog-to-digital converter (ADC) adopts a class-AB op-amp for the first integrator since it shows an enhanced slew rate with low quiescent current. In addition, a 4-bit asynchronous successive approximation register (SAR) ADC which exhibits low power consumption is employed as a quantizer. A delay is incorporated into the feedback path for stable operation of the feedback loop. The prototype ADC is fabricated in a 28 nm CMOS process, and the core area is 0.095 mm2. It consumes 12.3 μW from 0.8 V (Analog)/0.85 V (Digital) supply voltages at an operating clock frequency of 512 kHz with an oversampling ratio (OSR) of 256. It achieves a dynamic range (DR) of 97.7 dB and a peak signal-to-noise and distortion ratio (SNDR) of 94.8 dB, corresponding to a Schreier figure-of-merit (FoM) of 176.8 dB.
목차
Abstract
I. INTRODUCTION
II. ARCHITECTURE
III. CIRCUIT IMPLEMENTATION
IV. MEASUREMENT RESULTS
V. CONCLUSIONS
REFERENCES
참고문헌 (17)
참고문헌 신청
J. Silva, U. Moon, J. Steensguqrd, and G. C. Temes, “Wide band low distortion delta-sigma ADC topology,” IEE Electron. Lett., vol. 37, no.12, pp. 737-738, Jun. 2001.
K. Cho, Y. Kwak, H. Kim, and G. Ahn, “A 101dB dynamic range, 2kHz bandwidth delta-sigma modulator with a modified feedforward architecture,” IEICE Electron. Exp., vol. 15, no. 21, 2018, Art. no. 20180848.
Y. -J. Kim, H. -C. Choi, G. -C. Ahn and S. -H. Lee, "A 12 bit 50 MS/s CMOS Nyquist A/D Converter With a Fully Differential Class-AB Switched Op-Amp," in IEEE Journal of Solid-State Circuits, vol. 45, no. 3, pp. 620-628, March 2010.
M. S. Akter, R. Sehgal, F. van der Goes, K. A. A. Makinwa and K. Bult, "A 66-dB SNDR Pipelined Split-ADC in 40-nm CMOS Using a Class-AB Residue Amplifier," in IEEE Journal of Solid-State Circuits, vol. 53, no. 10, pp. 2939-2950, Oct. 2018.
J. -H. Boo et al., "A Single-Trim Switched Capacitor CMOS Bandgap Reference With a 3σ Inaccuracy of +0.02%, −0.12% for Battery-Monitoring Applications," in IEEE Journal of Solid-State Circuits, vol. 56, no. 4, pp. 1197-1206, April 2021.
K. Cho, Y. Kwak, H. Kim, and G. Ahn, “A 101dB dynamic range, 2kHz bandwidth delta-sigma modulator with a modified feedforward architecture,” IEICE Electron. Exp., vol. 15, no. 21, 2018, Art. no. 20180848.
Y. -J. Kim, H. -C. Choi, G. -C. Ahn and S. -H. Lee, "A 12 bit 50 MS/s CMOS Nyquist A/D Converter With a Fully Differential Class-AB Switched Op-Amp," in IEEE Journal of Solid-State Circuits, vol. 45, no. 3, pp. 620-628, March 2010.
M. S. Akter, R. Sehgal, F. van der Goes, K. A. A. Makinwa and K. Bult, "A 66-dB SNDR Pipelined Split-ADC in 40-nm CMOS Using a Class-AB Residue Amplifier," in IEEE Journal of Solid-State Circuits, vol. 53, no. 10, pp. 2939-2950, Oct. 2018.
J. -H. Boo et al., "A Single-Trim Switched Capacitor CMOS Bandgap Reference With a 3σ Inaccuracy of +0.02%, −0.12% for Battery-Monitoring Applications," in IEEE Journal of Solid-State Circuits, vol. 56, no. 4, pp. 1197-1206, April 2021.
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