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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 한국과학기술원 정보전자연구소 IDEC Journal of Integrated Circuits and Systems IDEC Journal of Integrated Circuits and Systems Vol.7 No.3
- 발행연도
- 2021.1
- 수록면
- 1 - 6 (6page)
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초록· 키워드
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This paper presents a 2.4 GHz sub-sampling fractional-N PLL (SSPLL) with a hybrid type phase-interpolator (HPI). The usage of the HPI alleviates the demanding specification of digi-tal-to-time converter (DTC). The proposed HPI structure is composed of a capacitive and tournament phase-interpolator (PI). This structure generates multi-phases with lower power consumption due to the capacitive PI part which do not con-sume the static power. On the other hand, the capacitive PI is affected by mismatches and parasitic when fine resolution is generated. In order to achieve accuracy with lower power con-sumption, MSB part is divided by capacitive PI and LSB part is divided by the tournament PI. The proposed SSPLL with the HPI is implemented by 65 nm CMOS process. It achieves 162 fs jitter, -247.3 dB figure-of-merit (FoM), and -47 dBc frac-tional spurs with a gain calibration circuit which is based on a least-mean-square (LMS) algorithm.
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참고문헌 (7)
참고문헌 신청
Gao, X. / 2009 / A Low Noise Sub-Sampling Pll in Which Divider Noise Is Eliminated and Pd/Cp Noise Is Not Multiplied by N-2 / IEEE Journal of Solid-State Circuits 44(12):3253~3263
Gao, X. A. / 2010 / Spur Reduction Techniques for Phase-Locked Loops Exploiting a Sub-Sampling Phase Detector / IEEE Journal of Solid-State Circuits 45(9):1809~1821
Markulic, N. / 2016 / A Dtc-Based Subsampling Pll Capable of Self-Calibrated Fractional Synthesis and Two-Point Modulation / IEEE Journal of Solid-State Circuits 51(12):3078~3092
Raczkowski, K. / 2015 / A 9. 2-12. 7 Ghz Wideband Fractional-N Subsampling Pll in 28 Nm Cmos with 280 Fs Rms Jitter / IEEE Journal of Solid-State Circuits 50(5):1203~1213
Tasca, D. / 2011 / A 2. 9-4. 0-Ghz Fractional-N Digital Pll with Bang-Bang Phase Detector and 560-Fs(Rms)Integrated Jitter at 4. 5-Mw Power / IEEE Journal of Solid-State Circuits 46(12):2745~2758
Gao, X. A. / 2010 / Spur Reduction Techniques for Phase-Locked Loops Exploiting a Sub-Sampling Phase Detector / IEEE Journal of Solid-State Circuits 45(9):1809~1821
Markulic, N. / 2016 / A Dtc-Based Subsampling Pll Capable of Self-Calibrated Fractional Synthesis and Two-Point Modulation / IEEE Journal of Solid-State Circuits 51(12):3078~3092
Raczkowski, K. / 2015 / A 9. 2-12. 7 Ghz Wideband Fractional-N Subsampling Pll in 28 Nm Cmos with 280 Fs Rms Jitter / IEEE Journal of Solid-State Circuits 50(5):1203~1213
Tasca, D. / 2011 / A 2. 9-4. 0-Ghz Fractional-N Digital Pll with Bang-Bang Phase Detector and 560-Fs(Rms)Integrated Jitter at 4. 5-Mw Power / IEEE Journal of Solid-State Circuits 46(12):2745~2758
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